It is often necessary in linear mixed-signal CMOS and BiCMOS integrated circuit devices to merge low-voltage (5 volts, for example) and high-voltage (10-15 volts, for example) CMOS devices. Generally, the low-voltage CMOS devices are used for digital logic, while the high-voltage CMOS devices are used in the analog portion of the circuit design.
One approach presently used to integrate low-voltage digital and high-voltage analog CMOS devices in a mixed-signal integrated circuit device is to use a conventional digital CMOS process to form both the low-voltage digital CMOS devices and the high-voltage analog CMOS devices. Conventional digital CMOS processes are designed to optimize digital performance by forming shallow source/drain (S/D) junctions, heavily doped twin-wells, and single-doped drain (SDD) NMOS devices. When such a process is used to form a mixed-signal CMOS or BiCMOS integrated circuit device, both the low-voltage digital CMOS devices and the high-voltage analog CMOS devices have shallow S/D junctions, heavily doped twin-wells, and SDD NMOS devices.
A drawback to the use of such conventional digital processes to integrate low-voltage digital and high-voltage analog CMOS devices in a mixed-signal integrated circuit device is the lack of reliability of the NMOS transistors in the high-voltage analog portion of the device when operated continuously at a high voltage (10-15 V) as required in most analog applications. This lack of reliability is due to hot-electron degradation attributable to the shallow junctions and the single impurity doping of the S/D regions of these NMOS transistors and the heavy doping of the P-wells in which these NMOS transistors are formed.
Another approach presently used to integrated low-voltage digital and high-voltage analog CMOS devices in a mixed-signal integrated circuit device is to use a conventional analog process. Conventional analog CMOS processes are designed to optimize analog performance by forming deep S/D junctions for higher curvature-induced breakdown voltages, lightly doped wells for lower S/D junction capacitance, and lightly-doped drain (LDD) transistors for improved hot-electron performance at the higher analog operating voltages. When such a process is used to form a mixed-signal CMOS or BiCMOS integrated circuit device, both the low-voltage digital CMOS devices and the high-voltage analog CMOS devices have deep S/D junctions, lightly doped wells, and LDD NMOS transistors.
A drawback to the use of such conventional analog processes to integrate low-voltage digital and high-voltage analog CMOS devices in a mixed-signal integrated circuit device is the susceptibility of the PMOS and NMOS transistors in the low-voltage digital portion of the device to short-channel problems, such as punch-through breakdown, when their channel lengths are scaled to less than approximately 2 microns.
A need therefore exists for a semiconductor device having both: 1.) low-voltage MOS devices having channel lengths scalable to less than 2 microns and 2.) reliable high-voltage MOS devices.